OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] - Rev 127

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 New config option to allow l.xori with unsigned operand. jeremybennett 5127d 11h /openrisc/
126 More explanation of l.xori. jeremybennett 5127d 12h /openrisc/
125 Update to specification of l.xori. jeremybennett 5127d 19h /openrisc/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5128d 07h /openrisc/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5128d 11h /openrisc/
122 Added l.ror and l.rori with associated tests. jeremybennett 5129d 07h /openrisc/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5129d 08h /openrisc/
120 Documents exception generation by l.jalr and l.jr jeremybennett 5129d 08h /openrisc/
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5129d 19h /openrisc/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5130d 05h /openrisc/
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5132d 07h /openrisc/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5132d 08h /openrisc/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5133d 08h /openrisc/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5133d 09h /openrisc/
113 Updates to exception handling for l.add and l.div jeremybennett 5134d 07h /openrisc/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5134d 07h /openrisc/
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5134d 12h /openrisc/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5135d 09h /openrisc/
109 or_debug_proxy does signals with signals, just ignores signals julius 5135d 17h /openrisc/
108 Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu. jeremybennett 5137d 07h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.