OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] - Rev 193

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
193 Record changes to initfini.c jeremybennett 5101d 00h /openrisc/
192 Updated to fix problems with initfini assembler fragments. jeremybennett 5101d 00h /openrisc/
191 Updated to clarify use of r9 in the l.jalr delay slot. jeremybennett 5101d 00h /openrisc/
190 Allow the Or1ksim installation directory to be set by option. jeremybennett 5101d 06h /openrisc/
189 Fuller explanation of the build script given. jeremybennett 5101d 06h /openrisc/
188 More rigorous testing of options. jeremybennett 5101d 07h /openrisc/
187 Or1200 sprs FPU update julius 5102d 23h /openrisc/
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5103d 02h /openrisc/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5103d 03h /openrisc/
184 Fix the UART version of newlib. jeremybennett 5104d 07h /openrisc/
183 Fix to setjmp, so it works. Some commenting tidy ups elsewhere. jeremybennett 5104d 23h /openrisc/
182 Removed redundant code. jeremybennett 5104d 23h /openrisc/
181 Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed. jeremybennett 5105d 02h /openrisc/
180 Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART. jeremybennett 5105d 02h /openrisc/
179 Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors. jeremybennett 5105d 02h /openrisc/
178 Fixes a bug in prologue recognition without frame pointer. jeremybennett 5105d 02h /openrisc/
177 Specified CPU type for or32, corrected templates for or32-*-elf*. Corrected specs in or32.h, added init and fini. Added support for newlib, including -mor32-newlib and -mor32-newlib-uart options. jeremybennett 5105d 02h /openrisc/
176 Removing empty and redundant directory. jeremybennett 5110d 04h /openrisc/
175 Moved orpmon into bootloaders julius 5110d 04h /openrisc/
174 Consolidating all RTOS ports in one directory. jeremybennett 5110d 05h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.