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Rev Log message Author Age Path
198 A collection of minor tidy ups. jeremybennett 5116d 09h /openrisc/
197 Fixed bug in memory allocator. jeremybennett 5118d 13h /openrisc/
196 Fixed name for newlib install option. jeremybennett 5118d 13h /openrisc/
195 Adding linux and uClibc paths back for patches, updated gnu-src build script making newlib an option (off by deafult) julius 5118d 13h /openrisc/
194 Tidied up code setjmp and longjmp into their own files, and adjusted Makefile accordingly. Simplified cache setup in startup code. Replaced calls via register with calls using immediate address. jeremybennett 5119d 07h /openrisc/
193 Record changes to initfini.c jeremybennett 5119d 07h /openrisc/
192 Updated to fix problems with initfini assembler fragments. jeremybennett 5119d 07h /openrisc/
191 Updated to clarify use of r9 in the l.jalr delay slot. jeremybennett 5119d 07h /openrisc/
190 Allow the Or1ksim installation directory to be set by option. jeremybennett 5119d 13h /openrisc/
189 Fuller explanation of the build script given. jeremybennett 5119d 13h /openrisc/
188 More rigorous testing of options. jeremybennett 5119d 13h /openrisc/
187 Or1200 sprs FPU update julius 5121d 06h /openrisc/
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5121d 09h /openrisc/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5121d 10h /openrisc/
184 Fix the UART version of newlib. jeremybennett 5122d 14h /openrisc/
183 Fix to setjmp, so it works. Some commenting tidy ups elsewhere. jeremybennett 5123d 06h /openrisc/
182 Removed redundant code. jeremybennett 5123d 06h /openrisc/
181 Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed. jeremybennett 5123d 09h /openrisc/
180 Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART. jeremybennett 5123d 09h /openrisc/
179 Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors. jeremybennett 5123d 09h /openrisc/

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