OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] - Rev 474

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
474 uC/OS-II port linker flags updated. julius 4887d 18h /openrisc/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 4888d 12h /openrisc/
472 Various changes which improve the quality of the tracing. jeremybennett 4888d 13h /openrisc/
471 Adding ucos-ii port. julius 4890d 16h /openrisc/
470 ORPSoC OR1200 crt0 updates. julius 4891d 12h /openrisc/
469 newlib update - added zeroing of r0 to crt0.S julius 4892d 13h /openrisc/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4892d 13h /openrisc/
467 ORPmon - bug fixes and clean up. julius 4893d 10h /openrisc/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README
julius 4893d 16h /openrisc/
465 ORPSoC SPI flash load Makefile and README updates. julius 4894d 06h /openrisc/
464 More ORPmon updates. julius 4894d 07h /openrisc/
463 ORPmon update julius 4894d 10h /openrisc/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4894d 15h /openrisc/
461 Updated to be much stricter about usage. jeremybennett 4896d 10h /openrisc/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4896d 12h /openrisc/
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4896d 18h /openrisc/
458 or1ksim testsuite updates julius 4897d 16h /openrisc/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4906d 06h /openrisc/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4906d 08h /openrisc/
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4910d 10h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.