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70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5352d 22h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5352d 23h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5355d 15h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5355d 18h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5375d 16h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5379d 22h /openrisc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5382d 17h /openrisc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5392d 14h /openrisc/
62 This material is part of the separate website downloads directory. jeremybennett 5403d 17h /openrisc/
61 The build directory should not be part of the SVN configuration. jeremybennett 5403d 18h /openrisc/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5410d 11h /openrisc/
59 Toolchain install script gcc patch change and gdb configure change julius 5431d 11h /openrisc/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5434d 10h /openrisc/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5439d 14h /openrisc/
56 adding generic pll model to orpsoc julius 5447d 16h /openrisc/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5450d 06h /openrisc/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5460d 13h /openrisc/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5478d 14h /openrisc/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5479d 10h /openrisc/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5493d 12h /openrisc/

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