OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.4.0/] [doc/] - Rev 783

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
135 Tagging the 0.4.0 stable release of Or1ksim jeremybennett 5088d 00h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
134 Updates for stable release 0.4.0 jeremybennett 5088d 00h /openrisc/trunk/or1ksim/doc/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5093d 21h /openrisc/trunk/or1ksim/doc/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5094d 16h /openrisc/trunk/or1ksim/doc/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5094d 20h /openrisc/trunk/or1ksim/doc/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5095d 17h /openrisc/trunk/or1ksim/doc/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5096d 14h /openrisc/trunk/or1ksim/doc/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5098d 17h /openrisc/trunk/or1ksim/doc/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5100d 17h /openrisc/trunk/or1ksim/doc/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5101d 18h /openrisc/trunk/or1ksim/doc/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5103d 17h /openrisc/trunk/or1ksim/doc/
104 Candidate release 0.4.0rc4 jeremybennett 5107d 01h /openrisc/trunk/or1ksim/doc/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5115d 19h /openrisc/trunk/or1ksim/doc/
100 Single precision FPU stuff for or1ksim julius 5115d 21h /openrisc/trunk/or1ksim/doc/
99 Bug in test evaluation for library fixed. jeremybennett 5120d 19h /openrisc/trunk/or1ksim/doc/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5121d 20h /openrisc/trunk/or1ksim/doc/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5136d 02h /openrisc/trunk/or1ksim/doc/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5137d 03h /openrisc/trunk/or1ksim/doc/
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5142d 18h /openrisc/trunk/or1ksim/doc/
91 Tidy up of some obsolete configuration code. jeremybennett 5149d 16h /openrisc/trunk/or1ksim/doc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.