OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.4.0rc2/] [cpu/] [or32/] - Rev 107

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5141d 21h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
104 Candidate release 0.4.0rc4 jeremybennett 5145d 05h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5153d 23h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
100 Single precision FPU stuff for or1ksim julius 5154d 01h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5160d 00h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5174d 06h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5175d 07h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
91 Tidy up of some obsolete configuration code. jeremybennett 5187d 21h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5187d 22h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5188d 21h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
80 Add missing configuration files to SVN. jeremybennett 5189d 00h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5519d 06h /openrisc/tags/or1ksim/or1ksim-0.4.0rc2/cpu/or32/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.