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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] - Rev 115

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Rev Log message Author Age Path
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5165d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5165d 19h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5166d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5169d 19h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
104 Candidate release 0.4.0rc4 jeremybennett 5173d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5181d 20h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
100 Single precision FPU stuff for or1ksim julius 5181d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5187d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5202d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5203d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
91 Tidy up of some obsolete configuration code. jeremybennett 5215d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5215d 19h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5216d 18h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
80 Add missing configuration files to SVN. jeremybennett 5216d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5547d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/

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