OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2/] [testsuite/] [test-code-or1k/] [inst-set-test/] - Rev 234

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5126d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
233 New softfloat FPU and testfloat sw for or1ksim julius 5127d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5175d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5175d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
122 Added l.ror and l.rori with associated tests. jeremybennett 5176d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5176d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5177d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5179d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5180d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5180d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5181d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5184d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
106 Removing old tests, pending addition of new ones. jeremybennett 5184d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5196d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5202d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5216d 17h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.		 jeremybennett 5219d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5230d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/test-code-or1k/inst-set-test/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.