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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] - Rev 124

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124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5203d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5203d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
122 Added l.ror and l.rori with associated tests. jeremybennett 5204d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5204d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5204d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5207d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5208d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5208d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5209d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5210d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5212d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
106 Removing old tests, pending addition of new ones. jeremybennett 5212d 02h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
104 Candidate release 0.4.0rc4 jeremybennett 5215d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5224d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
100 Single precision FPU stuff for or1ksim julius 5224d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
99 Bug in test evaluation for library fixed. jeremybennett 5229d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5230d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5244d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5245d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.		 jeremybennett 5247d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/

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