OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 487

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
487 ORPSoC main software makefile update julius 4877d 21h /openrisc/trunk/
486 ORPSoC updates, mainly software, i2c driver julius 4877d 21h /openrisc/trunk/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4882d 02h /openrisc/trunk/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4883d 00h /openrisc/trunk/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4885d 02h /openrisc/trunk/
482 Don't hardcode tool versions in help text olof 4886d 14h /openrisc/trunk/
481 OR1200 Update. RTL and spec. julius 4898d 09h /openrisc/trunk/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4899d 06h /openrisc/trunk/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4900d 06h /openrisc/trunk/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4901d 21h /openrisc/trunk/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4902d 06h /openrisc/trunk/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4902d 23h /openrisc/trunk/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4903d 01h /openrisc/trunk/
474 uC/OS-II port linker flags updated. julius 4903d 07h /openrisc/trunk/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 4904d 02h /openrisc/trunk/
472 Various changes which improve the quality of the tracing. jeremybennett 4904d 03h /openrisc/trunk/
471 Adding ucos-ii port. julius 4906d 06h /openrisc/trunk/
470 ORPSoC OR1200 crt0 updates. julius 4907d 01h /openrisc/trunk/
469 newlib update - added zeroing of r0 to crt0.S julius 4908d 02h /openrisc/trunk/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4908d 03h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.