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Rev Log message Author Age Path
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5208d 12h /openrisc/trunk/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5211d 03h /openrisc/trunk/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5211d 06h /openrisc/trunk/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5231d 04h /openrisc/trunk/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5235d 10h /openrisc/trunk/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5238d 05h /openrisc/trunk/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5248d 03h /openrisc/trunk/
62 This material is part of the separate website downloads directory. jeremybennett 5259d 06h /openrisc/trunk/
61 The build directory should not be part of the SVN configuration. jeremybennett 5259d 06h /openrisc/trunk/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5265d 23h /openrisc/trunk/
59 Toolchain install script gcc patch change and gdb configure change julius 5287d 00h /openrisc/trunk/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5289d 22h /openrisc/trunk/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5295d 02h /openrisc/trunk/
56 adding generic pll model to orpsoc julius 5303d 04h /openrisc/trunk/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5305d 19h /openrisc/trunk/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5316d 02h /openrisc/trunk/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5334d 02h /openrisc/trunk/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5334d 23h /openrisc/trunk/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5349d 01h /openrisc/trunk/
50 Adding or32_funcs.S julius 5349d 05h /openrisc/trunk/

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