OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] - Rev 437

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
437 Or1ksim - ethernet peripheral update, working much better. julius 4972d 14h /openrisc/trunk/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4973d 15h /openrisc/trunk/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4973d 15h /openrisc/trunk/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4976d 21h /openrisc/trunk/
433 New single program interrupt test programs. jeremybennett 4977d 23h /openrisc/trunk/
432 Updates to handle interrupts correctly. jeremybennett 4978d 00h /openrisc/trunk/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.
julius 4979d 23h /openrisc/trunk/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4980d 21h /openrisc/trunk/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 4981d 00h /openrisc/trunk/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4983d 20h /openrisc/trunk/
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 4985d 04h /openrisc/trunk/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 4986d 15h /openrisc/trunk/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 4986d 16h /openrisc/trunk/
424 C++ library, needed for C++ compiler. jeremybennett 4987d 02h /openrisc/trunk/
423 Minor typo fixed. jeremybennett 4987d 05h /openrisc/trunk/
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 4987d 05h /openrisc/trunk/
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".
julius 4990d 03h /openrisc/trunk/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4992d 01h /openrisc/trunk/
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.
julius 4992d 04h /openrisc/trunk/
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4992d 04h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.