OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 480

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4898d 01h /openrisc/trunk/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4899d 00h /openrisc/trunk/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4900d 16h /openrisc/trunk/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4901d 00h /openrisc/trunk/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4901d 17h /openrisc/trunk/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4901d 20h /openrisc/trunk/
474 uC/OS-II port linker flags updated. julius 4902d 02h /openrisc/trunk/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 4902d 20h /openrisc/trunk/
472 Various changes which improve the quality of the tracing. jeremybennett 4902d 22h /openrisc/trunk/
471 Adding ucos-ii port. julius 4905d 01h /openrisc/trunk/
470 ORPSoC OR1200 crt0 updates. julius 4905d 20h /openrisc/trunk/
469 newlib update - added zeroing of r0 to crt0.S julius 4906d 21h /openrisc/trunk/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4906d 21h /openrisc/trunk/
467 ORPmon - bug fixes and clean up. julius 4907d 19h /openrisc/trunk/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4908d 00h /openrisc/trunk/
465 ORPSoC SPI flash load Makefile and README updates. julius 4908d 15h /openrisc/trunk/
464 More ORPmon updates. julius 4908d 15h /openrisc/trunk/
463 ORPmon update julius 4908d 18h /openrisc/trunk/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4908d 23h /openrisc/trunk/
461 Updated to be much stricter about usage. jeremybennett 4910d 19h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.