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Rev Log message Author Age Path
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5377d 10h /openrisc/trunk/
56 adding generic pll model to orpsoc julius 5385d 12h /openrisc/trunk/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5388d 02h /openrisc/trunk/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5398d 09h /openrisc/trunk/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5416d 10h /openrisc/trunk/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5417d 06h /openrisc/trunk/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5431d 08h /openrisc/trunk/
50 Adding or32_funcs.S julius 5431d 12h /openrisc/trunk/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5450d 02h /openrisc/trunk/
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5450d 05h /openrisc/trunk/
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5459d 13h /openrisc/trunk/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5465d 13h /openrisc/trunk/
45 Orpsoc eth test fix and script error message update julius 5472d 13h /openrisc/trunk/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5501d 13h /openrisc/trunk/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5525d 10h /openrisc/trunk/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5541d 07h /openrisc/trunk/
41 Update to or1k top julius 5544d 08h /openrisc/trunk/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5545d 13h /openrisc/trunk/
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5549d 14h /openrisc/trunk/
38 Adding binutils, gcc, uClibc patched source and patches julius 5559d 13h /openrisc/trunk/

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