URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] - Rev 357

Rev	Log message	Author	Age	Path
357	Tidied up commenting.	jeremybennett	5169d 17h	/openrisc/trunk/gnu-old/gdb-7.1/sim/
244	Don't try to skip prologue using SAL info (fails with STABS). Fuller check of prologue. Change register names to rnn from gprnn to match assembler. Add debug option to simulator wrapper. * or32-tdep.c (or32_register_name): Changed to rnn rather than gprnn to mach the assembler. (or32_is_arg_reg, or32_is_callee_saved_reg): Added. (or32_skip_prologue): Don't use skip_prologue_using_sal. Check for argument as well as callee saved registers in prologue. (or32_frame_cache):Check for argument as well as callee saved registers in prologue. * wrapper.c: OR32_SIM_DEBUG added to control debug messages. (sim_close, sim_load, sim_create_inferior, sim_fetch_register) (sim_stop): Debug statement added. (sim_read, sim_write): Debug statements now controlled by OR32_SIM_DEBUG. (sim_store_register, sim_resume): Debug statement added and existing debug statements now controlled by OR32_SIM_DEBUG.	jeremybennett	5190d 15h	/openrisc/trunk/gnu-old/gdb-7.1/sim/
237	Fixes bug in handling single stepping.	jeremybennett	5206d 08h	/openrisc/trunk/gnu-old/gdb-7.1/sim/
232	Brought documentation up to date.	jeremybennett	5208d 13h	/openrisc/trunk/gnu-old/gdb-7.1/sim/
227	GDB 7.1 for OpenRISC 1000. Initial checkin.	jeremybennett	5210d 05h	/openrisc/trunk/gnu-old/gdb-7.1/sim/