OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] - Rev 429

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
357 Tidied up commenting. jeremybennett 5179d 14h /openrisc/trunk/gnu-src/gdb-7.1/
252 Changes to use source and line info when DWARF debug data is available. jeremybennett 5194d 10h /openrisc/trunk/gnu-src/gdb-7.1/
249 Corrected handling of double args to dummy calls. Better way of determining frame_id.

* or32-tdep.c (or32_push_dummy_call): Corrected handling of double
args provided in two regs.
(or32_frame_cache): Set frame_id based on SP as it will be, even
it not yet computed.		 jeremybennett 5195d 14h /openrisc/trunk/gnu-src/gdb-7.1/
248 Fixed two bugs in GDB tests.

* gdb.base/break.exp: Test for breakpoint at marker4, output
should be identical whether run with or without prototypes.
* gdb.base/call-sc.exp (test_scalar_returns): When the result of a
return is unknown, the value returned is undefined, not unchanged.		 jeremybennett 5195d 14h /openrisc/trunk/gnu-src/gdb-7.1/
244 Don't try to skip prologue using SAL info (fails with STABS). Fuller check of prologue. Change register names to rnn from gprnn to match assembler. Add debug option to simulator wrapper.

* or32-tdep.c (or32_register_name): Changed to rnn rather than
gprnn to mach the assembler.
(or32_is_arg_reg, or32_is_callee_saved_reg): Added.
(or32_skip_prologue): Don't use skip_prologue_using_sal. Check for
argument as well as callee saved registers in prologue.
(or32_frame_cache):Check for argument as well as callee saved
registers in prologue.

* wrapper.c: OR32_SIM_DEBUG added to control debug messages.
(sim_close, sim_load, sim_create_inferior, sim_fetch_register)
(sim_stop): Debug statement added.
(sim_read, sim_write): Debug statements now controlled by
OR32_SIM_DEBUG.
(sim_store_register, sim_resume): Debug statement added and
existing debug statements now controlled by OR32_SIM_DEBUG.		 jeremybennett 5200d 12h /openrisc/trunk/gnu-src/gdb-7.1/
237 Fixes bug in handling single stepping. jeremybennett 5216d 05h /openrisc/trunk/gnu-src/gdb-7.1/
232 Brought documentation up to date. jeremybennett 5218d 10h /openrisc/trunk/gnu-src/gdb-7.1/
229 Changes to allow GDB 7.1 tests to run and to remove a couple of $Id$ that were confusing SVN. jeremybennett 5219d 08h /openrisc/trunk/gnu-src/gdb-7.1/
227 GDB 7.1 for OpenRISC 1000. Initial checkin. jeremybennett 5220d 02h /openrisc/trunk/gnu-src/gdb-7.1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.