| Rev |
Log message |
Author |
Age |
Path |
| 868 |
Declare du_flush_pipe in or1200_top
Signed-off-by: Olof Kindgren <olof at opencores.org> |
olof |
3754d 07h |
/openrisc/trunk/or1200/rtl/ |
| 865 |
Raise illegal instruction exception when l.ror is not implemented
Instead of throwing an illegal instruction exception when the rotate
instructions are disabled (OR1200_ALU_IMPL_ROTATE is undefined), another
instruction (slr?) was executed instead.
This closes bug 97
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4085d 05h |
/openrisc/trunk/or1200/rtl/ |
| 859 |
Execute trapped instruction after breakpoint is removed
Closes bug #104
When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.
Proposed solution:
- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).
- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).
Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org> |
olof |
4198d 18h |
/openrisc/trunk/or1200/rtl/ |
| 852 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4430d 19h |
/openrisc/trunk/or1200/rtl/ |
| 847 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4445d 11h |
/openrisc/trunk/or1200/rtl/ |
| 846 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4445d 11h |
/openrisc/trunk/or1200/rtl/ |
| 845 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4445d 11h |
/openrisc/trunk/or1200/rtl/ |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4466d 04h |
/openrisc/trunk/or1200/rtl/ |
| 813 |
or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4480d 21h |
/openrisc/trunk/or1200/rtl/ |
| 808 |
OR1200: Add DSX bit support to SR.
Updated documentation, revision is now 13.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 |
julius |
4596d 15h |
/openrisc/trunk/or1200/rtl/ |
| 806 |
OR1200: Fix for bug 90
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4596d 15h |
/openrisc/trunk/or1200/rtl/ |
| 804 |
OR1200: Fix for bug 91
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4596d 15h |
/openrisc/trunk/or1200/rtl/ |
| 802 |
OR1200: Fix for bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4601d 20h |
/openrisc/trunk/or1200/rtl/ |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4635d 06h |
/openrisc/trunk/or1200/rtl/ |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4659d 20h |
/openrisc/trunk/or1200/rtl/ |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4683d 20h |
/openrisc/trunk/or1200/rtl/ |
| 674 |
or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled |
julius |
4726d 05h |
/openrisc/trunk/or1200/rtl/ |
| 644 |
or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled |
julius |
4864d 19h |
/openrisc/trunk/or1200/rtl/ |
| 643 |
or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix |
julius |
4864d 19h |
/openrisc/trunk/or1200/rtl/ |
| 642 |
or1200: add carry, overflow bits, and range exception |
julius |
4864d 19h |
/openrisc/trunk/or1200/rtl/ |
