| Rev |
Log message |
Author |
Age |
Path |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5015d 03h |
/openrisc/trunk/or1200/rtl/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5015d 13h |
/openrisc/trunk/or1200/rtl/ |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5016d 21h |
/openrisc/trunk/or1200/rtl/ |
| 352 |
OR1200 RTL DC sensitivity list fix |
julius |
5017d 18h |
/openrisc/trunk/or1200/rtl/ |
| 260 |
Fixed `define in FPU that didnt need to be there |
julius |
5023d 16h |
/openrisc/trunk/or1200/rtl/ |
| 259 |
Fixing or1200_defines FPU module selection defines - They are no longer needed |
julius |
5025d 12h |
/openrisc/trunk/or1200/rtl/ |
| 258 |
Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off |
julius |
5025d 13h |
/openrisc/trunk/or1200/rtl/ |
| 187 |
Or1200 sprs FPU update |
julius |
5075d 17h |
/openrisc/trunk/or1200/rtl/ |
| 186 |
OR1200 RTL FPU fix - RF writeback signal working properly again |
julius |
5075d 20h |
/openrisc/trunk/or1200/rtl/ |
| 185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5075d 21h |
/openrisc/trunk/or1200/rtl/ |
| 151 |
OR1200 rel3 (added some files that were not checked-in earlier) |
marcus.erlandsson |
5084d 16h |
/openrisc/trunk/or1200/rtl/ |
| 142 |
added OpenRISC version rel3 |
marcus.erlandsson |
5087d 01h |
/openrisc/trunk/or1200/rtl/ |
| 141 |
added OpenRISC version rel3 |
marcus.erlandsson |
5087d 01h |
/openrisc/trunk/or1200/rtl/ |
| 10 |
or1200 added from or1k subversion repository |
unneback |
5488d 04h |
/openrisc/trunk/or1200/rtl/ |
