URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] - Rev 302

Rev	Log message	Author	Age	Path
260	Fixed `define in FPU that didnt need to be there	julius	5192d 13h	/openrisc/trunk/or1200/rtl/verilog/
259	Fixing or1200_defines FPU module selection defines - They are no longer needed	julius	5194d 09h	/openrisc/trunk/or1200/rtl/verilog/
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5194d 09h	/openrisc/trunk/or1200/rtl/verilog/
187	Or1200 sprs FPU update	julius	5244d 13h	/openrisc/trunk/or1200/rtl/verilog/
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5244d 16h	/openrisc/trunk/or1200/rtl/verilog/
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5244d 17h	/openrisc/trunk/or1200/rtl/verilog/
151	OR1200 rel3 (added some files that were not checked-in earlier)	marcus.erlandsson	5253d 13h	/openrisc/trunk/or1200/rtl/verilog/
142	added OpenRISC version rel3	marcus.erlandsson	5255d 21h	/openrisc/trunk/or1200/rtl/verilog/
141	added OpenRISC version rel3	marcus.erlandsson	5255d 21h	/openrisc/trunk/or1200/rtl/verilog/
10	or1200 added from or1k subversion repository	unneback	5657d 01h	/openrisc/trunk/or1200/rtl/verilog/