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[/] [openrisc/] [trunk/] [or1ksim/] - Rev 227

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Rev Log message Author Age Path
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5061d 00h /openrisc/trunk/or1ksim/
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5061d 07h /openrisc/trunk/or1ksim/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5067d 23h /openrisc/trunk/or1ksim/
202 Adding executed log in binary format capability to or1ksim julius 5074d 03h /openrisc/trunk/or1ksim/
144 Missing file to fix bug 1797. jeremybennett 5091d 02h /openrisc/trunk/or1ksim/
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5091d 03h /openrisc/trunk/or1ksim/
134 Updates for stable release 0.4.0 jeremybennett 5099d 07h /openrisc/trunk/or1ksim/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5105d 04h /openrisc/trunk/or1ksim/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5105d 23h /openrisc/trunk/or1ksim/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5106d 03h /openrisc/trunk/or1ksim/
122 Added l.ror and l.rori with associated tests. jeremybennett 5106d 23h /openrisc/trunk/or1ksim/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5107d 00h /openrisc/trunk/or1ksim/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5107d 21h /openrisc/trunk/or1ksim/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5110d 00h /openrisc/trunk/or1ksim/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5111d 00h /openrisc/trunk/or1ksim/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5111d 01h /openrisc/trunk/or1ksim/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5111d 23h /openrisc/trunk/or1ksim/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5113d 01h /openrisc/trunk/or1ksim/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5115d 00h /openrisc/trunk/or1ksim/
106 Removing old tests, pending addition of new ones. jeremybennett 5115d 00h /openrisc/trunk/or1ksim/

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