OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 563

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4816d 00h /openrisc/trunk/or1ksim/
559 or1ksim - spr-def.sh fix for timer julius 4817d 12h /openrisc/trunk/or1ksim/
556 or1ksim - added performance counters unit and test for it. julius 4821d 18h /openrisc/trunk/or1ksim/
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4823d 03h /openrisc/trunk/or1ksim/
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4849d 23h /openrisc/trunk/or1ksim/
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4860d 19h /openrisc/trunk/or1ksim/
510 Updates for release 0.5.1rc1. jeremybennett 4881d 02h /openrisc/trunk/or1ksim/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4882d 02h /openrisc/trunk/or1ksim/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4923d 19h /openrisc/trunk/or1ksim/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4947d 04h /openrisc/trunk/or1ksim/
472 Various changes which improve the quality of the tracing. jeremybennett 4966d 05h /openrisc/trunk/or1ksim/
461 Updated to be much stricter about usage. jeremybennett 4974d 02h /openrisc/trunk/or1ksim/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4974d 03h /openrisc/trunk/or1ksim/
458 or1ksim testsuite updates julius 4975d 08h /openrisc/trunk/or1ksim/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4983d 22h /openrisc/trunk/or1ksim/
451 More tidying up. jeremybennett 4994d 18h /openrisc/trunk/or1ksim/
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4994d 22h /openrisc/trunk/or1ksim/
443 Work in progress on more efficient Ethernet. jeremybennett 5000d 02h /openrisc/trunk/or1ksim/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5000d 16h /openrisc/trunk/or1ksim/
440 Updated documentation to describe new Ethernet usage. jeremybennett 5001d 18h /openrisc/trunk/or1ksim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.