URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] - Rev 530

Rev	Log message	Author	Age	Path
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	5061d 05h	/openrisc/trunk/or1ksim/autom4te.cache/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5077d 23h	/openrisc/trunk/or1ksim/autom4te.cache/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5087d 20h	/openrisc/trunk/or1ksim/autom4te.cache/
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5098d 01h	/openrisc/trunk/or1ksim/autom4te.cache/
418	Or1ksim - adding new option when configuring memories, "exitnops"	julius	5106d 09h	/openrisc/trunk/or1ksim/autom4te.cache/
233	New softfloat FPU and testfloat sw for or1ksim	julius	5206d 21h	/openrisc/trunk/or1ksim/autom4te.cache/
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5210d 02h	/openrisc/trunk/or1ksim/autom4te.cache/
202	Adding executed log in binary format capability to or1ksim	julius	5223d 05h	/openrisc/trunk/or1ksim/autom4te.cache/
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5429d 05h	/openrisc/trunk/or1ksim/autom4te.cache/
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5641d 12h	/openrisc/trunk/or1ksim/autom4te.cache/