| Rev |
Log message |
Author |
Age |
Path |
| 233 |
New softfloat FPU and testfloat sw for or1ksim |
julius |
5206d 15h |
/openrisc/trunk/or1ksim/cpu/ |
| 230 |
Changed library interface. Fixed namespace problems with instruction lookup in library.
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int. |
jeremybennett |
5207d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 226 |
Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated |
julius |
5209d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 224 |
Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. |
jeremybennett |
5210d 04h |
/openrisc/trunk/or1ksim/cpu/ |
| 220 |
Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. |
jeremybennett |
5216d 19h |
/openrisc/trunk/or1ksim/cpu/ |
| 202 |
Adding executed log in binary format capability to or1ksim |
julius |
5222d 23h |
/openrisc/trunk/or1ksim/cpu/ |
| 143 |
Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). |
jeremybennett |
5240d 00h |
/openrisc/trunk/or1ksim/cpu/ |
| 127 |
New config option to allow l.xori with unsigned operand. |
jeremybennett |
5254d 00h |
/openrisc/trunk/or1ksim/cpu/ |
| 124 |
Overflow handling now in line with architecture manual. Tests added. |
jeremybennett |
5254d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 123 |
Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. |
jeremybennett |
5255d 00h |
/openrisc/trunk/or1ksim/cpu/ |
| 122 |
Added l.ror and l.rori with associated tests. |
jeremybennett |
5255d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 121 |
Adds exception handling to l.jalr and l.jr. Adds appropriate tests. |
jeremybennett |
5255d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 118 |
New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. |
jeremybennett |
5256d 17h |
/openrisc/trunk/or1ksim/cpu/ |
| 116 |
Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. |
jeremybennett |
5258d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 115 |
Added support for l.fl1 and tests for l.ff1 and l.fl1 |
jeremybennett |
5259d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 114 |
l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. |
jeremybennett |
5259d 21h |
/openrisc/trunk/or1ksim/cpu/ |
| 112 |
Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. |
jeremybennett |
5260d 20h |
/openrisc/trunk/or1ksim/cpu/ |
| 107 |
New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. |
jeremybennett |
5263d 21h |
/openrisc/trunk/or1ksim/cpu/ |
| 104 |
Candidate release 0.4.0rc4 |
jeremybennett |
5267d 04h |
/openrisc/trunk/or1ksim/cpu/ |
| 101 |
ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c |
jeremybennett |
5275d 22h |
/openrisc/trunk/or1ksim/cpu/ |
