OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 662

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4830d 16h /openrisc/trunk/or1ksim/cpu/
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4894d 15h /openrisc/trunk/or1ksim/cpu/
559 or1ksim - spr-def.sh fix for timer julius 4896d 02h /openrisc/trunk/or1ksim/cpu/
556 or1ksim - added performance counters unit and test for it. julius 4900d 08h /openrisc/trunk/or1ksim/cpu/
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4901d 17h /openrisc/trunk/or1ksim/cpu/
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4928d 13h /openrisc/trunk/or1ksim/cpu/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4960d 16h /openrisc/trunk/or1ksim/cpu/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5025d 18h /openrisc/trunk/or1ksim/cpu/
472 Various changes which improve the quality of the tracing. jeremybennett 5044d 19h /openrisc/trunk/or1ksim/cpu/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5052d 17h /openrisc/trunk/or1ksim/cpu/
458 or1ksim testsuite updates julius 5053d 22h /openrisc/trunk/or1ksim/cpu/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5062d 12h /openrisc/trunk/or1ksim/cpu/
440 Updated documentation to describe new Ethernet usage. jeremybennett 5080d 08h /openrisc/trunk/or1ksim/cpu/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5089d 03h /openrisc/trunk/or1ksim/cpu/
432 Updates to handle interrupts correctly. jeremybennett 5093d 12h /openrisc/trunk/or1ksim/cpu/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5096d 09h /openrisc/trunk/or1ksim/cpu/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 5096d 12h /openrisc/trunk/or1ksim/cpu/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5099d 08h /openrisc/trunk/or1ksim/cpu/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5107d 13h /openrisc/trunk/or1ksim/cpu/
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.
jeremybennett 5147d 13h /openrisc/trunk/or1ksim/cpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.