OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 143

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5254d 02h /openrisc/trunk/or1ksim/cpu/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5268d 02h /openrisc/trunk/or1ksim/cpu/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5268d 22h /openrisc/trunk/or1ksim/cpu/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5269d 02h /openrisc/trunk/or1ksim/cpu/
122 Added l.ror and l.rori with associated tests. jeremybennett 5269d 22h /openrisc/trunk/or1ksim/cpu/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5269d 22h /openrisc/trunk/or1ksim/cpu/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5270d 19h /openrisc/trunk/or1ksim/cpu/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5272d 22h /openrisc/trunk/or1ksim/cpu/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5273d 22h /openrisc/trunk/or1ksim/cpu/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5273d 23h /openrisc/trunk/or1ksim/cpu/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5274d 22h /openrisc/trunk/or1ksim/cpu/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5277d 22h /openrisc/trunk/or1ksim/cpu/
104 Candidate release 0.4.0rc4 jeremybennett 5281d 06h /openrisc/trunk/or1ksim/cpu/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5290d 00h /openrisc/trunk/or1ksim/cpu/
100 Single precision FPU stuff for or1ksim julius 5290d 02h /openrisc/trunk/or1ksim/cpu/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5296d 01h /openrisc/trunk/or1ksim/cpu/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5310d 07h /openrisc/trunk/or1ksim/cpu/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5311d 08h /openrisc/trunk/or1ksim/cpu/
91 Tidy up of some obsolete configuration code. jeremybennett 5323d 22h /openrisc/trunk/or1ksim/cpu/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5323d 23h /openrisc/trunk/or1ksim/cpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.