OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] - Rev 202

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 Adding executed log in binary format capability to or1ksim julius 5208d 16h /openrisc/trunk/or1ksim/cpu/or32/
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5225d 17h /openrisc/trunk/or1ksim/cpu/or32/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5239d 17h /openrisc/trunk/or1ksim/cpu/or32/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5240d 13h /openrisc/trunk/or1ksim/cpu/or32/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5240d 17h /openrisc/trunk/or1ksim/cpu/or32/
122 Added l.ror and l.rori with associated tests. jeremybennett 5241d 13h /openrisc/trunk/or1ksim/cpu/or32/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5241d 14h /openrisc/trunk/or1ksim/cpu/or32/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5242d 10h /openrisc/trunk/or1ksim/cpu/or32/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5244d 14h /openrisc/trunk/or1ksim/cpu/or32/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5245d 13h /openrisc/trunk/or1ksim/cpu/or32/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5245d 14h /openrisc/trunk/or1ksim/cpu/or32/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5246d 13h /openrisc/trunk/or1ksim/cpu/or32/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5249d 14h /openrisc/trunk/or1ksim/cpu/or32/
104 Candidate release 0.4.0rc4 jeremybennett 5252d 21h /openrisc/trunk/or1ksim/cpu/or32/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5261d 15h /openrisc/trunk/or1ksim/cpu/or32/
100 Single precision FPU stuff for or1ksim julius 5261d 17h /openrisc/trunk/or1ksim/cpu/or32/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5267d 16h /openrisc/trunk/or1ksim/cpu/or32/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5281d 22h /openrisc/trunk/or1ksim/cpu/or32/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5283d 00h /openrisc/trunk/or1ksim/cpu/or32/
91 Tidy up of some obsolete configuration code. jeremybennett 5295d 13h /openrisc/trunk/or1ksim/cpu/or32/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.