OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] - Rev 673

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4841d 16h /openrisc/trunk/or1ksim/doc/
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4905d 15h /openrisc/trunk/or1ksim/doc/
556 or1ksim - added performance counters unit and test for it. julius 4911d 09h /openrisc/trunk/or1ksim/doc/
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4912d 17h /openrisc/trunk/or1ksim/doc/
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4939d 13h /openrisc/trunk/or1ksim/doc/
510 Updates for release 0.5.1rc1. jeremybennett 4970d 17h /openrisc/trunk/or1ksim/doc/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4971d 17h /openrisc/trunk/or1ksim/doc/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 5013d 10h /openrisc/trunk/or1ksim/doc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5036d 19h /openrisc/trunk/or1ksim/doc/
472 Various changes which improve the quality of the tracing. jeremybennett 5055d 19h /openrisc/trunk/or1ksim/doc/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5063d 18h /openrisc/trunk/or1ksim/doc/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5073d 12h /openrisc/trunk/or1ksim/doc/
451 More tidying up. jeremybennett 5084d 08h /openrisc/trunk/or1ksim/doc/
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5084d 12h /openrisc/trunk/or1ksim/doc/
443 Work in progress on more efficient Ethernet. jeremybennett 5089d 16h /openrisc/trunk/or1ksim/doc/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5090d 07h /openrisc/trunk/or1ksim/doc/
440 Updated documentation to describe new Ethernet usage. jeremybennett 5091d 08h /openrisc/trunk/or1ksim/doc/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5100d 03h /openrisc/trunk/or1ksim/doc/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5103d 09h /openrisc/trunk/or1ksim/doc/
432 Updates to handle interrupts correctly. jeremybennett 5104d 12h /openrisc/trunk/or1ksim/doc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.