Rev |
Log message |
Author |
Age |
Path |
787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4552d 01h |
/openrisc/trunk/or1ksim/doc/ |
784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4553d 16h |
/openrisc/trunk/or1ksim/doc/ |
625 |
Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. |
jeremybennett |
4772d 23h |
/openrisc/trunk/or1ksim/doc/ |
561 |
or1ksim - timer module, spr-defs.h re-bugfix |
julius |
4836d 22h |
/openrisc/trunk/or1ksim/doc/ |
556 |
or1ksim - added performance counters unit and test for it. |
julius |
4842d 16h |
/openrisc/trunk/or1ksim/doc/ |
552 |
or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets |
julius |
4844d 00h |
/openrisc/trunk/or1ksim/doc/ |
538 |
or1ksim updates. spr-def.h updates, Cygwin compile error fixes. |
julius |
4870d 20h |
/openrisc/trunk/or1ksim/doc/ |
510 |
Updates for release 0.5.1rc1. |
jeremybennett |
4902d 00h |
/openrisc/trunk/or1ksim/doc/ |
508 |
Updates for Or1ksim 0.5.0rc3. |
jeremybennett |
4903d 00h |
/openrisc/trunk/or1ksim/doc/ |
494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
4944d 17h |
/openrisc/trunk/or1ksim/doc/ |
483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4968d 02h |
/openrisc/trunk/or1ksim/doc/ |
472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4987d 03h |
/openrisc/trunk/or1ksim/doc/ |
460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4995d 01h |
/openrisc/trunk/or1ksim/doc/ |
457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
5004d 19h |
/openrisc/trunk/or1ksim/doc/ |
451 |
More tidying up. |
jeremybennett |
5015d 16h |
/openrisc/trunk/or1ksim/doc/ |
450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
5015d 19h |
/openrisc/trunk/or1ksim/doc/ |
443 |
Work in progress on more efficient Ethernet. |
jeremybennett |
5021d 00h |
/openrisc/trunk/or1ksim/doc/ |
442 |
OR1Ksim - adding trace controlability by SIGUSR1 signal. |
julius |
5021d 14h |
/openrisc/trunk/or1ksim/doc/ |
440 |
Updated documentation to describe new Ethernet usage. |
jeremybennett |
5022d 15h |
/openrisc/trunk/or1ksim/doc/ |
436 |
Or1ksim ethernet TAP updates. Ethernet test still failing. |
julius |
5031d 10h |
/openrisc/trunk/or1ksim/doc/ |