OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] - Rev 99

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5203d 02h /openrisc/trunk/or1ksim/peripheral/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5217d 08h /openrisc/trunk/or1ksim/peripheral/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5218d 10h /openrisc/trunk/or1ksim/peripheral/
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5224d 00h /openrisc/trunk/or1ksim/peripheral/
91 Tidy up of some obsolete configuration code. jeremybennett 5230d 23h /openrisc/trunk/or1ksim/peripheral/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5231d 00h /openrisc/trunk/or1ksim/peripheral/
87 Typo fixed. jeremybennett 5231d 07h /openrisc/trunk/or1ksim/peripheral/
86 Bug 1723 fixed (PS2 keyboard error message clarification). jeremybennett 5231d 07h /openrisc/trunk/or1ksim/peripheral/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5231d 23h /openrisc/trunk/or1ksim/peripheral/
80 Add missing configuration files to SVN. jeremybennett 5232d 03h /openrisc/trunk/or1ksim/peripheral/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5350d 02h /openrisc/trunk/or1ksim/peripheral/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5562d 08h /openrisc/trunk/or1ksim/peripheral/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.