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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 54

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Rev Log message Author Age Path
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5344d 08h /openrisc/trunk/orpsocv2/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5362d 08h /openrisc/trunk/orpsocv2/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5363d 04h /openrisc/trunk/orpsocv2/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5377d 07h /openrisc/trunk/orpsocv2/
50 Adding or32_funcs.S julius 5377d 11h /openrisc/trunk/orpsocv2/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5396d 01h /openrisc/trunk/orpsocv2/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5411d 12h /openrisc/trunk/orpsocv2/
45 Orpsoc eth test fix and script error message update julius 5418d 11h /openrisc/trunk/orpsocv2/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5447d 11h /openrisc/trunk/orpsocv2/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5471d 08h /openrisc/trunk/orpsocv2/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5487d 05h /openrisc/trunk/orpsocv2/
41 Update to or1k top julius 5490d 06h /openrisc/trunk/orpsocv2/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5491d 12h /openrisc/trunk/orpsocv2/
36 Better clean rule in makefile julius 5505d 12h /openrisc/trunk/orpsocv2/
6 Checking in ORPSoCv2 julius 5509d 23h /openrisc/trunk/orpsocv2/

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