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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 55

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Rev Log message Author Age Path
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5321d 08h /openrisc/trunk/orpsocv2/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5331d 15h /openrisc/trunk/orpsocv2/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5349d 16h /openrisc/trunk/orpsocv2/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5350d 12h /openrisc/trunk/orpsocv2/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5364d 14h /openrisc/trunk/orpsocv2/
50 Adding or32_funcs.S julius 5364d 19h /openrisc/trunk/orpsocv2/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5383d 08h /openrisc/trunk/orpsocv2/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5398d 20h /openrisc/trunk/orpsocv2/
45 Orpsoc eth test fix and script error message update julius 5405d 19h /openrisc/trunk/orpsocv2/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5434d 19h /openrisc/trunk/orpsocv2/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5458d 16h /openrisc/trunk/orpsocv2/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5474d 13h /openrisc/trunk/orpsocv2/
41 Update to or1k top julius 5477d 14h /openrisc/trunk/orpsocv2/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5478d 19h /openrisc/trunk/orpsocv2/
36 Better clean rule in makefile julius 5492d 20h /openrisc/trunk/orpsocv2/
6 Checking in ORPSoCv2 julius 5497d 07h /openrisc/trunk/orpsocv2/

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