Rev |
Log message |
Author |
Age |
Path |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5240d 13h |
/openrisc/trunk/orpsocv2/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5250d 10h |
/openrisc/trunk/orpsocv2/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5292d 06h |
/openrisc/trunk/orpsocv2/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5297d 10h |
/openrisc/trunk/orpsocv2/ |
56 |
adding generic pll model to orpsoc |
julius |
5305d 12h |
/openrisc/trunk/orpsocv2/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5308d 03h |
/openrisc/trunk/orpsocv2/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5318d 10h |
/openrisc/trunk/orpsocv2/ |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5336d 10h |
/openrisc/trunk/orpsocv2/ |
52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5337d 06h |
/openrisc/trunk/orpsocv2/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5351d 09h |
/openrisc/trunk/orpsocv2/ |
50 |
Adding or32_funcs.S |
julius |
5351d 13h |
/openrisc/trunk/orpsocv2/ |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5370d 03h |
/openrisc/trunk/orpsocv2/ |
46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5385d 14h |
/openrisc/trunk/orpsocv2/ |
45 |
Orpsoc eth test fix and script error message update |
julius |
5392d 13h |
/openrisc/trunk/orpsocv2/ |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5421d 13h |
/openrisc/trunk/orpsocv2/ |
43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5445d 10h |
/openrisc/trunk/orpsocv2/ |
42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5461d 07h |
/openrisc/trunk/orpsocv2/ |
41 |
Update to or1k top |
julius |
5464d 08h |
/openrisc/trunk/orpsocv2/ |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5465d 14h |
/openrisc/trunk/orpsocv2/ |
36 |
Better clean rule in makefile |
julius |
5479d 14h |
/openrisc/trunk/orpsocv2/ |