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677 atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.

While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.

Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>
stekern 4650d 03h /openrisc/trunk/orpsocv2/
673 Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. yannv 4717d 05h /openrisc/trunk/orpsocv2/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4720d 20h /openrisc/trunk/orpsocv2/
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4720d 20h /openrisc/trunk/orpsocv2/
662 minor corrections to clean simulation files paknick 4747d 01h /openrisc/trunk/orpsocv2/
661 added makefile for icarus simulation paknick 4747d 01h /openrisc/trunk/orpsocv2/
660 updated makefiles for simulation with altera ordb2a-ep4ce22 paknick 4747d 04h /openrisc/trunk/orpsocv2/
656 orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used julius 4771d 22h /openrisc/trunk/orpsocv2/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4771d 22h /openrisc/trunk/orpsocv2/
652 Fix make compile.tcl for actel backend yannv 4780d 05h /openrisc/trunk/orpsocv2/
651 ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.

Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi>
julius 4785d 00h /openrisc/trunk/orpsocv2/
650 ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups julius 4785d 22h /openrisc/trunk/orpsocv2/
638 orpsoc: xilinx: use XILINX env variable

instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4826d 15h /openrisc/trunk/orpsocv2/
634 orpsoc: atlys: autoregenerate coregen cores

Instead of keeping binary .ngc files of the coregen
generated cores, use coregen to generate them from the .xco
and .cgp file
stekern 4831d 15h /openrisc/trunk/orpsocv2/
633 orpsoc: add Digilent Atlys spartan6 board README

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/
632 orpsoc: add Digilent Atlys spartan6 board sw include file

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/
631 orpsoc: add Digilent Atlys spartan6 board testbench

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/
630 orpsoc: add Digilent Atlys spartan6 board backend

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/
629 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/
628 orpsoc: add Digilent Atlys spartan6 board Makefiles

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4831d 15h /openrisc/trunk/orpsocv2/

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