Rev |
Log message |
Author |
Age |
Path |
351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5082d 06h |
/openrisc/trunk/orpsocv2/ |
350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5082d 10h |
/openrisc/trunk/orpsocv2/ |
349 |
ORPSoCv2 update with new software and makefile update |
julius |
5082d 10h |
/openrisc/trunk/orpsocv2/ |
348 |
First stage of ORPSoCv2 update - more to come |
julius |
5082d 10h |
/openrisc/trunk/orpsocv2/ |
185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5140d 08h |
/openrisc/trunk/orpsocv2/ |
111 |
Changed conditionals for Verilator to "verilator" instead of "VERILATOR". |
jeremybennett |
5172d 10h |
/openrisc/trunk/orpsocv2/ |
78 |
Fixed typo in Silos workaround script |
rherveille |
5235d 05h |
/openrisc/trunk/orpsocv2/ |
77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5235d 05h |
/openrisc/trunk/orpsocv2/ |
76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5236d 05h |
/openrisc/trunk/orpsocv2/ |
71 |
ORPSoC board builds, adding readmes |
julius |
5278d 15h |
/openrisc/trunk/orpsocv2/ |
70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5282d 19h |
/openrisc/trunk/orpsocv2/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5282d 20h |
/openrisc/trunk/orpsocv2/ |
68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5285d 12h |
/openrisc/trunk/orpsocv2/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5285d 15h |
/openrisc/trunk/orpsocv2/ |
66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5305d 13h |
/openrisc/trunk/orpsocv2/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5309d 19h |
/openrisc/trunk/orpsocv2/ |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5312d 14h |
/openrisc/trunk/orpsocv2/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5322d 11h |
/openrisc/trunk/orpsocv2/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5364d 07h |
/openrisc/trunk/orpsocv2/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5369d 11h |
/openrisc/trunk/orpsocv2/ |