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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 62

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Rev Log message Author Age Path
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5375d 20h /openrisc/trunk/orpsocv2/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5381d 00h /openrisc/trunk/orpsocv2/
56 adding generic pll model to orpsoc julius 5389d 03h /openrisc/trunk/orpsocv2/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5391d 17h /openrisc/trunk/orpsocv2/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5402d 00h /openrisc/trunk/orpsocv2/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5420d 01h /openrisc/trunk/orpsocv2/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5420d 21h /openrisc/trunk/orpsocv2/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5434d 23h /openrisc/trunk/orpsocv2/
50 Adding or32_funcs.S julius 5435d 03h /openrisc/trunk/orpsocv2/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5453d 17h /openrisc/trunk/orpsocv2/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5469d 04h /openrisc/trunk/orpsocv2/
45 Orpsoc eth test fix and script error message update julius 5476d 04h /openrisc/trunk/orpsocv2/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5505d 03h /openrisc/trunk/orpsocv2/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5529d 00h /openrisc/trunk/orpsocv2/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5544d 21h /openrisc/trunk/orpsocv2/
41 Update to or1k top julius 5547d 23h /openrisc/trunk/orpsocv2/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5549d 04h /openrisc/trunk/orpsocv2/
36 Better clean rule in makefile julius 5563d 04h /openrisc/trunk/orpsocv2/
6 Checking in ORPSoCv2 julius 5567d 16h /openrisc/trunk/orpsocv2/

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