| Rev |
Log message |
Author |
Age |
Path |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5102d 03h |
/openrisc/trunk/orpsocv2/ |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5102d 05h |
/openrisc/trunk/orpsocv2/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5103d 03h |
/openrisc/trunk/orpsocv2/ |
| 350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5103d 07h |
/openrisc/trunk/orpsocv2/ |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5103d 07h |
/openrisc/trunk/orpsocv2/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5103d 07h |
/openrisc/trunk/orpsocv2/ |
| 185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5161d 05h |
/openrisc/trunk/orpsocv2/ |
| 111 |
Changed conditionals for Verilator to "verilator" instead of "VERILATOR". |
jeremybennett |
5193d 07h |
/openrisc/trunk/orpsocv2/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5256d 02h |
/openrisc/trunk/orpsocv2/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5256d 02h |
/openrisc/trunk/orpsocv2/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5257d 02h |
/openrisc/trunk/orpsocv2/ |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5299d 12h |
/openrisc/trunk/orpsocv2/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5303d 16h |
/openrisc/trunk/orpsocv2/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5303d 17h |
/openrisc/trunk/orpsocv2/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5306d 09h |
/openrisc/trunk/orpsocv2/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5306d 12h |
/openrisc/trunk/orpsocv2/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5326d 10h |
/openrisc/trunk/orpsocv2/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5330d 16h |
/openrisc/trunk/orpsocv2/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5333d 11h |
/openrisc/trunk/orpsocv2/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5343d 08h |
/openrisc/trunk/orpsocv2/ |
