URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 52

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5479d 10h	/openrisc/trunk/orpsocv2/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5493d 13h	/openrisc/trunk/orpsocv2/
50	Adding or32_funcs.S	julius	5493d 17h	/openrisc/trunk/orpsocv2/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5512d 06h	/openrisc/trunk/orpsocv2/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5527d 18h	/openrisc/trunk/orpsocv2/
45	Orpsoc eth test fix and script error message update	julius	5534d 17h	/openrisc/trunk/orpsocv2/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5563d 17h	/openrisc/trunk/orpsocv2/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5587d 14h	/openrisc/trunk/orpsocv2/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5603d 11h	/openrisc/trunk/orpsocv2/
41	Update to or1k top	julius	5606d 12h	/openrisc/trunk/orpsocv2/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5607d 18h	/openrisc/trunk/orpsocv2/
36	Better clean rule in makefile	julius	5621d 18h	/openrisc/trunk/orpsocv2/
6	Checking in ORPSoCv2	julius	5626d 05h	/openrisc/trunk/orpsocv2/