| Rev |
Log message |
Author |
Age |
Path |
| 864 |
ORPSoC: Merge display_arch_state tasks
or1200-monitor contains the tasks display_arch_state and display_arch_state_except which are almost identical. This patch merges these two tasks into one, with a parameter to specify whether it should print out "(exception)" or not
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
4177d 11h |
/openrisc/trunk/orpsocv2/bench/ |
| 863 |
ORPSoC: Add paramers to or1200-monitor for setting name and path of log files
Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
4183d 15h |
/openrisc/trunk/orpsocv2/bench/ |
| 862 |
sysc: avoid using orpsoc internal classes directly
The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api. |
stekern |
4194d 07h |
/openrisc/trunk/orpsocv2/bench/ |
| 861 |
sysc: include unistd.h
write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail |
stekern |
4194d 07h |
/openrisc/trunk/orpsocv2/bench/ |
| 860 |
or1200_monitor.v: Remove trailing whitespace |
olof |
4198d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4659d 15h |
/openrisc/trunk/orpsocv2/bench/ |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4813d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
5039d 19h |
/openrisc/trunk/orpsocv2/bench/ |
| 495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
5042d 22h |
/openrisc/trunk/orpsocv2/bench/ |
| 493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
5056d 00h |
/openrisc/trunk/orpsocv2/bench/ |
| 491 |
ORPSoC or1200_monitor update. |
julius |
5057d 09h |
/openrisc/trunk/orpsocv2/bench/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5074d 00h |
/openrisc/trunk/orpsocv2/bench/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5094d 04h |
/openrisc/trunk/orpsocv2/bench/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5100d 01h |
/openrisc/trunk/orpsocv2/bench/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
5102d 03h |
/openrisc/trunk/orpsocv2/bench/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
5113d 20h |
/openrisc/trunk/orpsocv2/bench/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5126d 15h |
/openrisc/trunk/orpsocv2/bench/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5133d 19h |
/openrisc/trunk/orpsocv2/bench/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5140d 10h |
/openrisc/trunk/orpsocv2/bench/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5153d 10h |
/openrisc/trunk/orpsocv2/bench/ |
