| Rev |
Log message |
Author |
Age |
Path |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5231d 05h |
/openrisc/trunk/orpsocv2/bench/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5231d 06h |
/openrisc/trunk/orpsocv2/bench/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5234d 00h |
/openrisc/trunk/orpsocv2/bench/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5253d 22h |
/openrisc/trunk/orpsocv2/bench/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5258d 04h |
/openrisc/trunk/orpsocv2/bench/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5260d 23h |
/openrisc/trunk/orpsocv2/bench/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5270d 20h |
/openrisc/trunk/orpsocv2/bench/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5317d 20h |
/openrisc/trunk/orpsocv2/bench/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5328d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5356d 20h |
/openrisc/trunk/orpsocv2/bench/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5357d 16h |
/openrisc/trunk/orpsocv2/bench/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5371d 19h |
/openrisc/trunk/orpsocv2/bench/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5390d 13h |
/openrisc/trunk/orpsocv2/bench/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5406d 00h |
/openrisc/trunk/orpsocv2/bench/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5441d 23h |
/openrisc/trunk/orpsocv2/bench/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5481d 17h |
/openrisc/trunk/orpsocv2/bench/ |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5486d 00h |
/openrisc/trunk/orpsocv2/bench/ |
| 6 |
Checking in ORPSoCv2 |
julius |
5504d 11h |
/openrisc/trunk/orpsocv2/bench/ |
