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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 60

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Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5324d 14h	/openrisc/trunk/orpsocv2/bench/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5335d 07h	/openrisc/trunk/orpsocv2/bench/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5363d 15h	/openrisc/trunk/orpsocv2/bench/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5364d 11h	/openrisc/trunk/orpsocv2/bench/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5378d 13h	/openrisc/trunk/orpsocv2/bench/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5397d 07h	/openrisc/trunk/orpsocv2/bench/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5412d 18h	/openrisc/trunk/orpsocv2/bench/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5448d 17h	/openrisc/trunk/orpsocv2/bench/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5488d 11h	/openrisc/trunk/orpsocv2/bench/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5492d 18h	/openrisc/trunk/orpsocv2/bench/
6	Checking in ORPSoCv2	julius	5511d 06h	/openrisc/trunk/orpsocv2/bench/

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