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Rev Log message Author Age Path
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5366d 07h /openrisc/trunk/orpsocv2/bench/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5369d 02h /openrisc/trunk/orpsocv2/bench/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5378d 23h /openrisc/trunk/orpsocv2/bench/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5425d 23h /openrisc/trunk/orpsocv2/bench/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5436d 15h /openrisc/trunk/orpsocv2/bench/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5464d 23h /openrisc/trunk/orpsocv2/bench/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5465d 19h /openrisc/trunk/orpsocv2/bench/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5479d 21h /openrisc/trunk/orpsocv2/bench/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5498d 15h /openrisc/trunk/orpsocv2/bench/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5514d 02h /openrisc/trunk/orpsocv2/bench/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5550d 02h /openrisc/trunk/orpsocv2/bench/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5589d 20h /openrisc/trunk/orpsocv2/bench/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5594d 02h /openrisc/trunk/orpsocv2/bench/
6 Checking in ORPSoCv2 julius 5612d 14h /openrisc/trunk/orpsocv2/bench/

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