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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 57

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57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5332d 21h /openrisc/trunk/orpsocv2/bench/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5343d 13h /openrisc/trunk/orpsocv2/bench/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5371d 21h /openrisc/trunk/orpsocv2/bench/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5372d 17h /openrisc/trunk/orpsocv2/bench/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5386d 19h /openrisc/trunk/orpsocv2/bench/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5405d 13h /openrisc/trunk/orpsocv2/bench/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5421d 01h /openrisc/trunk/orpsocv2/bench/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5457d 00h /openrisc/trunk/orpsocv2/bench/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5496d 18h /openrisc/trunk/orpsocv2/bench/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5501d 00h /openrisc/trunk/orpsocv2/bench/
6 Checking in ORPSoCv2 julius 5519d 12h /openrisc/trunk/orpsocv2/bench/

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