URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] - Rev 52

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5334d 06h	/openrisc/trunk/orpsocv2/bench/sysc/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5348d 08h	/openrisc/trunk/orpsocv2/bench/sysc/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5367d 02h	/openrisc/trunk/orpsocv2/bench/sysc/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5418d 13h	/openrisc/trunk/orpsocv2/bench/sysc/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5458d 07h	/openrisc/trunk/orpsocv2/bench/sysc/
6	Checking in ORPSoCv2	julius	5481d 01h	/openrisc/trunk/orpsocv2/bench/sysc/