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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] - Rev 285

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Rev Log message Author Age Path
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5302d 09h /openrisc/trunk/orpsocv2/bench/sysc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5325d 02h /openrisc/trunk/orpsocv2/bench/sysc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5332d 04h /openrisc/trunk/orpsocv2/bench/sysc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5342d 01h /openrisc/trunk/orpsocv2/bench/sysc/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5389d 00h /openrisc/trunk/orpsocv2/bench/sysc/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5428d 01h /openrisc/trunk/orpsocv2/bench/sysc/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5428d 21h /openrisc/trunk/orpsocv2/bench/sysc/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5442d 23h /openrisc/trunk/orpsocv2/bench/sysc/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5461d 17h /openrisc/trunk/orpsocv2/bench/sysc/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5513d 03h /openrisc/trunk/orpsocv2/bench/sysc/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5552d 21h /openrisc/trunk/orpsocv2/bench/sysc/
6 Checking in ORPSoCv2 julius 5575d 16h /openrisc/trunk/orpsocv2/bench/sysc/

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