URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] - Rev 53

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5336d 21h	/openrisc/trunk/orpsocv2/bench/sysc/include/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5350d 23h	/openrisc/trunk/orpsocv2/bench/sysc/include/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5369d 17h	/openrisc/trunk/orpsocv2/bench/sysc/include/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5421d 03h	/openrisc/trunk/orpsocv2/bench/sysc/include/
6	Checking in ORPSoCv2	julius	5483d 16h	/openrisc/trunk/orpsocv2/bench/sysc/include/