URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] - Rev 63

Rev	Log message	Author	Age	Path
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5247d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5334d 03h	/openrisc/trunk/orpsocv2/bench/sysc/include/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5348d 05h	/openrisc/trunk/orpsocv2/bench/sysc/include/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5366d 23h	/openrisc/trunk/orpsocv2/bench/sysc/include/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5418d 10h	/openrisc/trunk/orpsocv2/bench/sysc/include/
6	Checking in ORPSoCv2	julius	5480d 22h	/openrisc/trunk/orpsocv2/bench/sysc/include/