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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] - Rev 72

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Rev Log message Author Age Path
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5264d 00h /openrisc/trunk/orpsocv2/bench/sysc/include/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5271d 01h /openrisc/trunk/orpsocv2/bench/sysc/include/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5280d 22h /openrisc/trunk/orpsocv2/bench/sysc/include/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5367d 18h /openrisc/trunk/orpsocv2/bench/sysc/include/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5381d 20h /openrisc/trunk/orpsocv2/bench/sysc/include/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5400d 14h /openrisc/trunk/orpsocv2/bench/sysc/include/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5452d 01h /openrisc/trunk/orpsocv2/bench/sysc/include/
6 Checking in ORPSoCv2 julius 5514d 13h /openrisc/trunk/orpsocv2/bench/sysc/include/

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