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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] - Rev 373

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Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5182d 08h	/openrisc/trunk/orpsocv2/bench/sysc/include/
362	ORPSoCv2 verilator building working again. Board build fixes to follow	julius	5183d 18h	/openrisc/trunk/orpsocv2/bench/sysc/include/
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5185d 22h	/openrisc/trunk/orpsocv2/bench/sysc/include/
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5186d 01h	/openrisc/trunk/orpsocv2/bench/sysc/include/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5410d 06h	/openrisc/trunk/orpsocv2/bench/sysc/include/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5417d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5427d 04h	/openrisc/trunk/orpsocv2/bench/sysc/include/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5514d 00h	/openrisc/trunk/orpsocv2/bench/sysc/include/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5528d 02h	/openrisc/trunk/orpsocv2/bench/sysc/include/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5546d 20h	/openrisc/trunk/orpsocv2/bench/sysc/include/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5598d 07h	/openrisc/trunk/orpsocv2/bench/sysc/include/
6	Checking in ORPSoCv2	julius	5660d 19h	/openrisc/trunk/orpsocv2/bench/sysc/include/

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