URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 56

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5480d 20h	/openrisc/trunk/orpsocv2/bench/sysc/src/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5481d 17h	/openrisc/trunk/orpsocv2/bench/sysc/src/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5495d 19h	/openrisc/trunk/orpsocv2/bench/sysc/src/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5514d 13h	/openrisc/trunk/orpsocv2/bench/sysc/src/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5565d 23h	/openrisc/trunk/orpsocv2/bench/sysc/src/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5605d 17h	/openrisc/trunk/orpsocv2/bench/sysc/src/
6	Checking in ORPSoCv2	julius	5628d 11h	/openrisc/trunk/orpsocv2/bench/sysc/src/